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Ap European History Summer Assignment 2012. Dustin Winski Jun 26th, 2012 AP Euro AP European History Summer Assignment 2012 Why did trade and travel decline after the fall of Rome? After the fall of Rome, with no government to supply protection or to keep the thesis rads and bridges repaired, travel became difficult and dangerous. This danger, coupled with ignorance and essay, lack of desire to thesis change the situation by the powerful lords, whose manors required little trade, led to communication the decline in travel and thesis, trade. Who was the first “Holy Roman Emperor” and essay questions, how did he get that title? After restoring Pope Leo III in Rome from which he had been driven by invaders, Charlemagne was crowned by thesis, the Poe as “Emperor of the Romans”. The Frankish Kingdom them became known as the Holy Roman Empire, a name that would remain until the Empire was dissolved by Napoleon in 1806. Nurses Role Essay? What is the thesis difference between the in a lab report Roman Empire and the Holy Roman Empire? The Holy Roman Empire was started by Charlemagne and thesis, was centered in thiosulphate, France.

It was called the Holy Roman Empire#8221; due to the fact that the Pope crowned Charlemagne as the Emperor. What were the thesis connections between “The Holy Roman Empire” and “The Church”? The Holy Roman Empire was an essay endeavor by the Catholic Church and Christian kings to restore in journal, their own image the crumbled remains of the compare and contrast essay secular achievements of the ancient pagan Roman Empire. Define feudalism and describe the thesis characteristics of its organization. Feudalism was also a social and economics organization based on essay, a series of thesis, reciprocal relationships.

The king in theory owned the land which he granted to references lab report lords who in return would give service, usually in the form of thesis journal, military aid, to the king. For both, since the King#8217;s writ didn#8217;t extend directly through a country, they were often reliant on local governing mechanisms. In A? In practice, that usually meant the thesis nobility of the region involved, whose loyalty was to their own family and in health promotion, its privileges rather than to the monarchy. What were the thesis benefits supposedly derived from the feudal system? Who benefited the most? Feudal manors provided both political and essay on stereotypes of asian, social organization. Thesis? They also were individual economics units , nearly self-sufficient due to medieval warfare, the on stereotypes of asian difficulties to thesis journal travel, and off a essay with, the resultant lack of trade. The feudal estate featured a manor-home, usually a fortified castle surrounded by protective walls, belonging to journal the lord, surrounded by thiosulphate coursework, fields, herds and villages where serfs lived and thesis, worked. What was the importance of questions, “The Church” and the Christian religion in the lives of the Europeans in thesis journal, the Middle Ages? Religion and essay of asian, the after-life became the focal point of thought and living. The influence of religion can also clearly be seen in the art, architecture, literature, and journal, music of the references in a time.

This was most likely cause because life was so hard on thesis journal, earth, the value peasants endured it concentrating on and longing for their reward in the after-life. How did the journal ritual and sacraments of the communication essay questions Church establish a constant, ongoing relationship with its individual members? The believers of the Roman Catholic Church believed the seven sacraments kept an individual constantly connected to God and the Church from birth to death. The Church led the journal belief that one could only get to heaven through good deeds and observing the sacraments. How did the can you off a essay Church us the powers of excommunication and interdiction in maintaining its power?

The idea of journal, excommunicating individuals kept people from cons of cloning essay observing the sacraments which gave them the ability to enter heaven. Also, whole geographic areas could be punished through interdiction which prohibited the performance of any of the sacraments in journal, that district. This made the Church more organized than any other political state in acid, Europe. How was Education, learning and knowledge of thesis, Europe preserved during the lowest point of the Middle Ages, the so-called “Dark Ages”? Education was secured by value of solitude, the people being put into strict division of thesis, social classes most notably the Church, peasants, and the bourgeoisie. What was the role promotion essay dominant philosophy of the thesis journal Middle Ages called?

Who was its most outstanding spokesman? What were its basic beliefs, and how did the nurses philosophy view life and thesis, understanding? The dominant philosophy of the references late Middle Ages was best articulated by St. Thomas Aquinas and known as scholasticism. Who belonged to journal each of the essay three estates of medieval European society and what was the primary duty of thesis, a member of each estate? How was this different from the essay questions social classes in thesis, modern society? The first of the estates were composed of the Church.

The main purpose for can you with this estate would be to claim the journal authority of God. The second estate consisted of the communication nobility of #8216;society#8217;. The primary focus of the nobility were to function as warriors. Thesis? The third estate had little to no power in thiosulphate hydrochloric coursework, that time of society and composed of peasants and laymen. Journal? This changed throughout Europe with the coming of feudalism. This differs from essay with modern society for the facts of journal, a more prosperous middle class.

Describe the guilds. Who made up their membership and lab report, what was their influence on thesis journal, the business practices of the late Middle Ages? In the middle ages, the #8216;Guilds#8217; were labor market intermediaries organizing training, working conditions. These merchants and craftsmen formed the basis for a new class of townspeople, the bourgeoisie. They would be the basis of the growing middle class. How did the guilds improve the lot of of solitude essay, freemen? How did they help business and trade?

How did they restrict its growth? The improvement of the thesis freemen could be seen from role essay a point of their increase of professions. Thesis Journal? The benefits of this system would be the systematic control and increase of essay on stereotypes, certain professions that were needed at thesis, the time. This order was kept to maintain employment and necesity for the freemen. However, as a result of the of cloning humans essay control over journal the market, restrictions on compare, personal choice ended up restricting its growth. Who were the bourgeoisie? Why did they not fit in journal, the traditional class structure of the Middle Ages? The bourgeoisie were merchants and craftsmen formed the basis for a new class of town dwellers.

They did not fit into what would be considered traditional because of their system and plans of growing the lab report middle class. Why was the journal social structure of Europe challenged by the growing number of of solitude essay, free townspeople and thesis, the changing economy? With the strengthening control of the kings, powers and essay a quote, influence of the feudal lords led to leaving more land in the hands of fewer people. This led to the even farther decline in the idea of feudalism. How did the Crusades help to thesis journal begin the cons of cloning humans essay change from Medieval society into a modern society? The Crusades stimulated trade by certain political, social, and economic changes. This was achieved by thesis, the unknowing attacks on nurses promotion essay, feudal lords and in turn gave the increased power to the kings. The changes developed after the old nobility lacked the wealth to keep up with the kings. Why are the journal Crusades sometimes called “Successful failures”?

The Crusaders led to the eventual fading out of feudal states in the most of nurses role in health promotion, Europe and is an important part of thesis journal, European expansion and colonialism. Why and in what ways did kings and central governments grow stronger at the end of the Middle Ages? The Kings helped facilitate the communication questions forming of countries by uniting small feudal states into large kingdoms. Journal? They helped develop the idea of a central government within these kingdoms. This centralized government was indeed stronger than the smaller micro-state governments . Compare And Contrast Essay? What obstacles stood in the way of the creation of strong central governments? Since strong central governments often emerge from weaker central governments or loose confederations a central government may also have to thesis deal with regional lords who regard centralization as an infringement on their own ower.

Why was the re-establishment of trade so important to on stereotypes the transformation of Europe? Re-establishment of journal, trade was very important due to the fact of the bourgeoisie wanting to create a wider middle class. Hydrochloric Coursework? This could not happen because of what current state Europe was in journal, due to essay questions the idea of thesis journal, feudalism. Essay? Also, where there is any contact between two civilizations ideas will be traded amongst them, giving each civilization new ideas. Haven’t found what you want?

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logic design resume Seeking a challenging and rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in thesis journal, ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and of solitude essay, Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in SystemC and verified the TCP RTL implementation Designed and Verified ZBT SRAM and Flash interface for LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for thesis Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and Synthesised the same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of cons humans a Smart Card ASIC Participated in thesis journal, the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Electrical and Electronics Engineering. Created a detailed test-plan to verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per in health, the test plan Designed a Word Builder for journal the FC -1 block, integrated in the FC-1 RTL and verified the same. Verified the RTL implementation of TCP/IP Stack. A detailed test plan was created and SystemC models of the functional blocks were written to test the nurses in health promotion whole of TCP/IP Implementation. Designed and verified the LEXRA RISC Processor Interface with the functional blocks and verified the same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor.

Integrated all functional RTL modules and created a system level top. Perl scripts where written to manage the thesis files and test cases. Created the Vera testbench environment for the whole chip. Modified the SPI-4 soft core both on the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and implement the netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the of cloning essay RTL and post layout netlist for functionality and timing. Ingress FPGA for line card: Designed and journal, implemented the Network Processor interface on the Ingress traffic flow towards the Switch fabric.

The module also implements policing, segmentation, Packet format modifications and sends the packets across to the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to on stereotypes of asian Xilinx virtex II series XC2V3000 . Thesis? Gate count of the complete Ingress FPGA 1,800,000 gates. Compare Essay? Modified the Accelar Simulation Environment Nortel functional simulation environment used for Verification used the thesis same to verify the modified RTL code and synthesized gate level netlist. Essay On Stereotypes? The job involved understanding the journal Accelar simulation environment and modifying the cons same in accordance with the new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment. Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of thesis Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Designed testbench to test the DesignWare 8051 functionality. Mapped to whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and compare and contrast essay and outline, Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment.

SOC integration of Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Thesis? Project managed the whole simulation work of the compare and contrast essay and outline USB-Smart Card. Thesis Journal? Enhanced already present Smart Card Device Model. Responsible for testing debugging of the functionality of the design. USB SIE Serial Interface Engine : Designed tested of cons essay all the modules of Serial Interface Engine. Project managed the whole simulation work of the Serial Interface Engine. Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment.

Responsible for testing debugging of the thesis journal functionality of the SIE USBC design. Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in the kernel development of the simulator. Design and references, implemented an intermediate format for journal the simulator. Wrote extensive test cases to test the various constructs and expressions of VHDL according to and contrast SPEC defined by IEEE. References Furnished Upon Request. Development simulation/verification or design on high speed electronics. VHDL, C, MTI simulator, ModelSim, RiscWatch debugger.

Digital Corp. San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an journal existing PowerPC 603 cpu simulation model to communicate between an ASIC and a C code simulator, including the nurses role in health essay addition of decoders, latches, and state-machine modifications. Designed VHDL logic code that enhanced the 603 cpu model by journal, generating an internal address bus busy signal when an address-only phase is initiated by the ASIC. Developed 200+ C testcases for functional simulation, system level stressing and value essay, debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers. Co-developed C code for parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Thesis Journal? Developed test plans to nurses verify functionality of the ASIC s internal cache, and its 603 bus logic. Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers. Simpson Communications Corp.

White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of thesis data into value bytes, then calculates the average byte value from 16 bytes of data. Translated PAL gray-code state machine and thesis journal, counter ABEL equation designs into behavioral and start a quote, structural VHDL code then functionally simulated using Unix-based Synopsys tools. Translated gray-code state machine and thesis journal, counter state graph designs into nurses RTL and thesis, structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools. Start With? Developed a C code program that calculates a least-sum path of distances squared for thesis a trade study that will implement ATM networking hardware on a RF communications data link. Researched and wrote a white paper about Voice over ATM using AAL1 CBR, AAL2 rt-VBR AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for networking over a RF communications data link. Amtel Corp.

Boxsboro, OR. Configured and validated the compatibility of various PCI and EISA LANs and SCSI controllers and compare and outline, devices on thesis journal, quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. ME Electrical Engineering, University of Utah, Salt Lake City, UT. BS Electrical Engineering, University of Utah, Salt Lake City, UT. TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU.

TARGET JOB: Telecommunications, Medical, Underwater Research and R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year. Site Location: On-Site.

Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER. Career Level: Management Manager/Director of Staff. Date of Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering.

TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in this country for any employer. Role In Health? Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to thesis a group of 20 Engineer and Manufacturing Personnel. Nurses In Health Promotion? Provided upper management monthly Progress Reports and journal, Weekly Departmental updates.

Interacted with all required agencies, vendors, and customers to meet corporate objectives and deadlines. Extensive expertise in the Engineering Process. Compare And Contrast? Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in thesis, providing Technical Engineering Leadership and of asian, Support to System, Concept, Equipment, Readiness and Production Review in Transiting new Designs into a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of thesis various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in essay on stereotypes, generation of Assembly Dwgs., Parts Lists, Detailed Dwgs. Altered Item Dwgs.

Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Thesis Journal? Integration and Test of a variety of cons humans Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager. Responsible for opening and thesis journal, closing.

Assignment of nurses promotion daily retail task and scheduling of available manpower. Providing customers with benefits of thesis journal my expertise in the Art of Woodworking. Lab Report? Upgraded and re-merchandise entire store increasing net sales by 30 . Have sold well over 250,000 woodworking tools in 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and thesis journal, developing all types of Photographic Media including Digital Photography. Essay? Handing of journal Customer questions and accountable for cash flow. Value Of Solitude? Expertise acquired in the service and maintenance of journal Fuji Photo Processing Equipment.

Generated documentation of all Photo Processing and Printing Procedures. Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in assessing and on stereotypes, performing the overall Functional and journal, In-Circuit Test activities in the production and repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms. Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards.

Documented and Performed Functional Test Procedure for essay of asian TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of thesis MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and cons of cloning essay, Cost Account Manager. Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Managed and participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and journal, security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and off a essay with, maintained PATRIOT COMO Simulation Laboratory.

Technical Integration Lead to an engineering group of 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. Technical Lead Integration Test Engineer for journal the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at compare and outline Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and thesis journal, Production Reviews. Assistant Subcontract Manager for essay on stereotypes of asian Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for thesis journal TACIT Rainbow Mission Computer TRMC . The TRMC is based upon in a a MC68030 with dual MC68332s along with two subsystems interface modules and thesis, a power supply.

Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and essay of asian, Production Reviews transiting the TRMC Design into a solid Product with the help of thesis journal Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required. Built, Serviced and nurses in health essay, Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in the performance of software code development, system simulation and software performance evaluations.

TRMC 80 Logic in Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into thesis journal the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates. Assigned design tasks and maintained cost and schedule.

Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Of Cloning? Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Tested and qualified to MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Lead Engineer for Dynamic Software Test Facility DSTF for thesis software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for innovative subsystem development. Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and essay, the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM.

Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and thesis journal, VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer.

Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in all phases of references electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon thesis journal the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic.

Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the start with i ncorporation of a wide range of thesis journal Off-the-Shelf Multibus I Modules. DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Worked in the Missile Integration and Test Department of the nurses role in health essay Missile Guidance Laboratory while attending NU. Assisted in the integration and testing of the journal prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings.

Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and cons humans, Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at thesis journal Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY.

1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS. 1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in compare essay, SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE. Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology.

Headed the design team in thesis journal, the implementation of the chip. Nurses Promotion Essay? VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into thesis an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and of cloning humans, an ITE PCI bridge. In charge of engineering development of board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for thesis journal PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.

Incorporated manufacturability into designs including ATE. Developed and maintained project schedules. Interfaced with the software department for BIOS and POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to essay on stereotypes of asian February, 1999. MANAGER OF ENGINEERING. Manager of the hardware engineering team. Involved in product planning for a new family of OEM image processing controllers.

These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and thesis, CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the essay on stereotypes of asian system architecture for a second ASIC that became the system intelligence. Journal? This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Nurses Role? Led the design efforts on this second ASIC. Journal? Both ASICs were in the 1M to 1.5 M gate range and implemented in cons of cloning essay, .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for journal different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to can you December, 1997.

MANAGER OF ENGINEERING. Managed the Raid Division engineering team. Responsibilities included scheduling, budgeting and journal, product development for both board and system level Raid products. Involved in defining the next generation architecture of in a lab report Raid controllers that was comprised of thesis journal a four ASIC chip set. In A? Project Manager for a Digital Equipment Corp. Thesis? specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and Digital doing the mechanical packaging.

Responsibilities included coordinating the hardware efforts between the in a lab report two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by thesis, Digital. Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and references lab report, the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering. CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of thesis a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology.

Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates. Value Of Solitude Essay? Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of journal DRAM buffering and FLASH EEPROM. Joined the essay Arcuate Scan Tape group and journal, designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology.

Also designed the Servo Gate detection ASIC used for of solitude head positioning. All ASICs designed and simulated at Conner were done using VHDL. IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments. Thesis Journal? Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration.

Defined future products and initial marketing strategies. Designed a proprietary Error Detection and cons essay, Correction ASIC to be used in memory intensive products. Journal? A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates. CAD tools used in these ASIC designs include Cadence for schematic capture and essay, Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in journal, setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA. October, 1984 to November, 1988.

PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on value, to the new system. Designed a 68000 based CPU board for this development system. Journal? During the design phase of the CPU, research was done on references, interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of thesis journal communication between the CPU and references in a lab report, intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol.

TRIANON CORPORATION, Sacramento, CA. March, 1981 to journal October, 1984. PROJECT MANAGER/SENIOR ENGINEER. Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project. Designed the cons of cloning humans essay hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface.

The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for thesis the micro-engine. The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in the development of compare essay and outline a new processor and the related I/O controllers. Designed the interface protocol and an I/O relay controller for this processor. Journal? This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon compare and contrast and outline receiving a pre or post trigger.

The back-end contained the necessary handshaking to a modem so the journal board may be used remotely from the operator. Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977. Concentration in Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of can you off a essay with a quote instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and thesis journal, micro controllers.

Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and smart work. Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date. Development of a stand alone device to references in a lab report measure moisture content of various agricultural products. Involved in Design and development of automatic moisture meter both independent and thesis journal, computer interfacable.

First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Design and coded same using C. Handled design and fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. The input taken by sensor directly displayed in compare essay and outline, terms of percentage moisture. Development of journal calibration technique based on method of least squares. Value? Writing source code and journal, test benches in VHDL for interfacing of 64K RAM, ROM, decoder and essay on stereotypes of asian, their interfacing with the A/D converter and PGA.

Simulation of calibration process and verification of functionality and journal, timing errors for same. Synthesizing code on can you off a essay with a quote, Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer.

Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for thesis the ALU to perform various arithemetic and logical opeartions. Cons Of Cloning? Source code for the RAM and journal, ROM entity was written and debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. a memory mapped output port was also added to the design.

Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools. Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to cons operate at 2.5 GHZ using spice simulation software.Involed in counter design for thesis the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and cons, area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters.

Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of thesis journal Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an value embedded processor. Enabled signal processing for digital applications. Worked in thesis journal, a team for simulation of chip. Carried out chip verification using using tools from mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from on stereotypes of asian, sigma Electronics, Mentor graphics tools, VHDL, Windows 98.

Technology mission for oil seeds and pulses. Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to be measured for different parameters. The selection of photodiodes was done to opearte at radio frequencies.

Designed analog and digital board around SPICE simulation software. Interfaced memory and thesis journal, display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Can You Start Off A Essay? Further, an FPGA was developed to perform the thesis journal application of microcontroller 8051 and the entire calibration circuit was interfaced around the compare Xilinx FPGA. Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts.

Department of thesis Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer. Designed and developed a 8-bit microprocessor. The device consists of references in a lab report a RAM, ROM, a high speed ALU, shifting, decoding and thesis journal, multiplexing circuitry. Made package for the instruction set of 8085 in VHDL. Wrote source code for the ALU to compare and outline perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the functionality of the processor using test benches on journal, Active HDL simulation package in Window NT environment. Essay? synthesized the thesis journal same on XILINX FPGA. Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses.

Digital aflatoxin meter Test Engineer. Designed electronics related to and contrast essay system around ORCAD IV , checked for the functionality of the journal design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of know how and essay on stereotypes, providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997. Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD. Checked the functionality of the journal same and its interfacing with the sensor. Documentation of instrument.

Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry. Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Responsible for lab report working with clients on intensive short term methodology training. Thesis? Responsible for training students in VHDL, synthesis and methodology. Aid in adaptation of training materials and development of new training classes. Cons Humans? Paper publications and presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and oil seedsin various national journals. Training has been imparted to various engineers and students of engineering colleges from time to time.

Significant contribution in organization of various seminars and conferences related to thesis journal instruments developed, various projects for essay of asian water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for thesis a TtME (Time to Market Engineering - a design verification consulting service) project for role in health a Germany based company. Successful completion of the project lead to the sale of an emulation system. Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and journal, debugging simulation differences.

Implemented Verification Flow. Identified introduced Cadence tools to the Verification process. In Health Promotion Essay? Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and thesis, provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and in health, test bench, and helped with the execution.

Assisted in customer evaluation (San Jose based IC design company for thesis journal DTVs) for a simulation acceleration beta product. Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in essay, sales for numerous simulation software licenses. Worked closely with Quickturn RD and a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s RD to integrate all of these products. Provided post-sales technical support and worked to increase the thesis simulation performance.

Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for cons humans maximum performance optimizations. Thesis Journal? Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to of cloning essay be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim.

Assisted the thesis Quickturn India Distributor with a customer evaluation. Compare And Outline? Responsibilities included going on site and using test bench methods, passing vectors for showing proof of Speedsim functionality and journal, performance on of asian, their design. Provided training to Application Engineers on topics related to thesis simulation/acceleration tools during boot camps and compare, other training sessions. Worked on thesis, numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools. Presented demos and presentations at DAC 98 and DAC 00. Corporate Technical Support Specialist: Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions.

Providing workarounds to customer issues and working with RD to value of solitude get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of thesis Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL. The unit included microprocessor and memory components.

Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in cons of cloning essay, Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl.

References available on request. ASIC PHYSICAL DESIGN ENGINEER. To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design. Area of journal specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in on stereotypes, short : Have got more than 20 months of experience in the field of VLSI.

Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti! Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to create testcases for QA of Avanti tools. Creating testcases to check various releases of Avanti tools.

Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs. Thesis Journal? Writing Test benches for designs. Writing Scripts to check the designs.

Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Essay A Quote? Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from journal, Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of and contrast essay skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of thesis journal each macro and the Top Cell. Can You Start Essay? (Tool used ApolloII). Journal? Physical Verification for DRC LVS for nurses role in health essay each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of thesis journal 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of nurses promotion 98.5%.

Contains 19 hard macros, and thesis, 28k standard cells. Can You Start Essay With A Quote? (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an thesis journal initial slack of -61.3, and congestion overflow of compare and contrast and outline 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. Journal? BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to value essay meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP)

EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in thesis, a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to compare essay make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to thesis journal read data, perform limited calculation on that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. EXPLORERTL for essay RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the journal following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated.

TOOLS USED : simulator : MODEL SIM PE 5.3b. DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious.

A go-getter. Essay? Quest for perfection in all assignments. Date of Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and journal, Standards: Digital wrapper (ITU-T G.709 standard) for FEC in can you start off a essay with, 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date.

Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and journal, a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force.

Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to of solitude essay support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Thesis Journal? Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Value Essay? Analyzed system requirement specifications and developed architecture for full functionality of the thesis chip. Compare And Contrast? Automated critical parts of design verification using VERA HVL.

Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation. October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an thesis journal FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface.

Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Of Cloning? Spectra interface consists of Transport OverHead (TOH) and thesis, Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on nurses role promotion essay, HMVIP side is sent to corresponding Spectra155 devices.

Similarly overhead data that is sent by Spectra155 device is sent to thesis HMVIP interface in start off a essay with, correct time slot at correct frame location. There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and journal, developed architecture for full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for lab report synthesis of design and generating sdf file. Did post-synthesis simulation of this design.

Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to thesis journal Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and cons essay, POS-PHY-3 bus on either side to convert data (packets) from journal, one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to of cloning humans carry Fcells in thesis journal, both receiver and transmit side.

Did regression testing of Verilog RTL code. Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and references lab report, Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from journal, XGA to UXGA and to even support SXGA+ and W-UXGA. Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for nurses role in health promotion essay digital transmission of thesis Video output data at of cloning humans 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor.

Involved in digital architecture design of chip. Coded the entire architecture in VHDL and journal, did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code). Used Synopsis DC for synthesis. Performed post-synthesis simulations. Tested and verified actual performance of chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1.

May 1999 - November 1999. Design of Flying Adder Digital Logic for role in health promotion PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to thesis journal maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in essay of asian, design of Digital logic for Flying Adder PLL (50MHz to 350MHz). Did coding of digital logic in VHDL. Performed synthesis of journal design using Synopsis DC. Nurses In Health? Used SPICE for analysis the analog behaviour of timing critical nets. Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1.

January 1999 - April 1999. Design of Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to thesis support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz).

Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Lab Report? Used Cadence Artist and Spice for analog design. Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in journal, the Design of a TMDS receiver core chip for LCD monitors. It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for references in a Power Management Module in VHDL.

Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998. Design of Single Phase Energy Meter. Designed and thesis journal, developed an start with Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis.

Did assembly language programming of design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in FPGA Design ASIC Verification. Proficient with coding RTL Behavioral using Verilog and thesis journal, VHDL. Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language. Proficient in writing fully automated test benches.

Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on compare essay and outline, Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys). Worked on thesis, Mentor Graphics Schematic Entry Tool – Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an of cloning ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol. Familiar with AMBA Bus Architecture.

Familiar with 8085 and 8086 Architecture. Journal? Familiar with 8085 Assembly Language. Essay A Quote? Familiar with software languages C and journal, Fortran. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of Project: Network Processor Verification. Wrote test plan for on stereotypes of asian one of the modules in the chip.

Developed the thesis journal test bench for the module. Compare? Wrote test cases in Verilog. Developed the different interfaces around the module. This network processor is thesis, designed to references provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of journal Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.

Designed and Synthesized SWATH cycle Controller module. RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify Developed the different interfaces around the Link 2 FPGA. Developed test plan for the functional verification and wrote test cases in Verilog. Done the module level verifications and top-level verification. Reported bugs and role in health promotion, worked with the design team in fixing the bugs.

This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. Journal? This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. Essay? This module does interface controlling from the input side and takes the processed data to thesis journal and from of solitude essay, SDRAM controller. This module also does the journal interface to the output swath FPGA. References? This Link2 acts as a link between the input FPGA and thesis, SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool).

Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level.

Wrote test cases in 'e' language and verified them using Modelsim simulator. Reported several bugs in the design and worked with the in a lab report designers to fix those bugs. The is a trace receiver, which provides the journal trace recording capabilities for one of the and contrast Emulation controller. The key features of the trace system ASIC are: Provides a maximum of 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of a minimum of thesis journal 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels. On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels.

This memory is used as channel temporary buffers and scratch memory when SDRAM is used to promotion store channel data. Thesis Journal? trace packet width from 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and in a lab report, a back end. The front end (TPFE)acquires the trace data presented by the target and thesis journal, packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and cons, host access to these buffers independent of whether the storing process is active. In short, the TPFE contains the acquisition, packing and journal, buffering functions while the essay on stereotypes TPBE distributes the TPFE generated data into thesis Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for test cases.

Engineering Design Center , Bangalore, INDIA. Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for signal Processing. Designed the Hardware . Designed the FPGA CPLD . Nurses Role Promotion? Done the functional simulation synthesis. Done extensive timing simulation with back annotating the journal sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and of asian, data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Journal? Only one of these may be activated at a given time. The design goal is to of asian accept data rate upto 40MB/s, but the journal testing will be limited to 20 MB/s transfer to memory. FPGA we were using was Spartan series XCS 40-4 ns.

VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in the Xilinx tool. Off A Essay? We are using Xilinx tool as the journal back end. Here we place and route the design and references in a, generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the thesis internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. So when timing simulation comes we load our design file and essay, the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the journal system side, it cannot be a permanent data as from EPROM.

So we are using the CPLD to configure the lab report FPGA. It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of journal UART.

Developed the architecture Designed and done RTL coding in essay and outline, VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in detail one Standard HDL Study in detail about the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project. Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance valuable contribution to the verification of Rrishti-1. Doing part-time courses in San Jose University for. Course 1- Advanced Logic Design (Winter 2001)

Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth.

H/W Description Languages: VHDL, Verilog. Thesis Journal? Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Of Asian? Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Languages: C, C++, perl, Unix Internals like Shell and Awk.

Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and journal, implementing software and hardware systems required to cons humans validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup. Worked closely with the ASIC and hardware development teams with the goal of thesis journal delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy.

Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and in a, real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and journal, SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and and contrast, final silicon lab verification environment. Thesis Journal? Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for essay that input vectors. The expected Value is checked with the RTL value to verify the functionality of thesis journal each block. Wrote high level monitors and stimulus models to automate the verification process. Analyzed the cons of cloning timing for Data Windows using Logic Analyzer thus reducing the time for journal Data Window writes from value of solitude essay, 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform. Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in estimating verification development schedules and ensured on time delivery.

Infotech Systems Inc., Boston, MA. As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the thesis digital portion of the chip for value of solitude essay television. Responsible for journal complete cycle from specification through design and test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA.

Developed simulations with VHDL and can you off a, simulated it in thesis, Modelsim generating the test vectors for testing the FPGA. Developed Verilog testbenches and tested the circuit back annotating with SDF. Checked the timing of the design generating test vectors for and outline testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA.

Developed test benches in VHDL for testing the proper working of the thesis journal design using Modelsim. Designed and tested the read channel chip. In A? Worked on three different versions of the read channel. Thesis? Designed the and contrast and outline FPGA using Visual HDL generating the RTL for thesis the design. Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip. Evaluated the design to test the read channel chip with various FPGA place and route tools.

Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and tested the compare Test Access Port (TAP) controller using Visual HDL. Designed an IEEE standard TAP controller. Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL. Simulated it using Modelsim. Developed Perl script for journal conversion of Spice netlist in to VERILOG netlist. The script written in references lab report, perl takes in a Spice netlist and gives the Verilog netlist. Developed testbenches for the Verilog netlist for the million-gate chip.

Developed test sequence for this verilog file for checking the operation of the chip. Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of thesis a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Other Projects Design of of cloning essay a Linear Interpolation Filter using Verilog and journal, full custom IC layout. Design of a Simple Educational Processor using VHDL.

Designed and simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer. To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on of asian, the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in thesis, Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and references, programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance.

Good communication and interpersonal skills. Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and journal, able to work in a team. Bachelor of Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for value essay networking purpose on journal, networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Fiber Optics.

My Role: As a team member I was involved in. FPGA ASIC design Wrote verilog HDL code for design. Wrote test bench for verification in C Used PLI for communication with Verilog. Integration testing verification. Cons Of Cloning Humans Essay? Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000. The objective of this project was to design, developed the data networking boards and test benches for verification purpose of pre written functions in verilog . Simulation and thesis, hardware development of communication subsystems using the sections reconfigurable-prototyping. Design, simulate, and test digital hardware.

Developed data networking boards, and backplanes. Performed the design, capture the references in a schematics and oversee the board layout. Thesis? Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99.

Client: FDD Container (UK) The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of value essay Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by thesis journal, the tech called DSP motioncontroll (Digital Signal Processing). On Stereotypes? The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. The code was written in c inline Assembly on Host Computer. Design, simulate, and test. Programming of journal SRAM DRAM. Writing Test Benches for Verification in verilog C. On Stereotypes Of Asian? Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Journal? Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98.

The purpose of the project was to design and develop micro controller chip 8051EB for references controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Which receives the signals from Boiler sensors. If due to any reason the temperature goes below specified level the journal alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by of solitude, c inline assembly. Device programmer was used to copy the image files on the chip. Design, simulate, and test micro controller chip.

Programmed SRAM DRAM. Wrote verification code in verilog C Performed the design, capture the thesis schematics and oversee the board layout. Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of material required and its Costing, providing an compare and contrast and outline easy access to feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of modifying as per the user specifications and standards. It takes the Complete Details of a building (to be constructed) by journal, providing an Interface and Calculates the references in a lab report quantity of material required with its estimated cost, as per the standards specified.

It provides an easy access for modifications. Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for thesis Microsoft Windows95 and Microsoft Windows NT, to be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. And Outline? Developed system allows you to get detailed Information with Graphical Representation related to an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an journal employee, and of cloning humans, its related information. Which intern Automatically updates the thesis journal related Schedules of essay with a quote other employees if desired. Environment: Visual C++, MS Windows 95.

Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the thesis journal Core Part is handled using C++, and the GUI (Graphical User Interface) is handled using Visual C++ for of cloning humans essay Microsoft Windows 95 and thesis, Microsoft Windows NT. Humans Essay? Which allows the user to maintain its File System with Security, providing File and Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of thesis journal Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Executing. Provides File Viewing facility before editing the files, giving an Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95.

Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at nurses essay the Printing and Advertising Companies as the thesis major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Can You Start Essay? Was a member of the team, which designed the system?

Other responsibilities included coding and thesis journal, testing. Can You Start Off A With A Quote? Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on journal, request. Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform. References In A Lab Report? Expertise in writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in Verilog/VHDL. Thesis Journal? Good knowledge of PCI protocol.

Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for essay of asian Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date. Verification of PCI bridge( PCI to journal local) PCI 9656. Wrote random tests for of cloning humans the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the thesis journal slave on the PCI bus, Direct master means that the chip is the nurses role promotion essay master on the PCI bus. Worked on PCI compliance testing for thesis journal the PCI 9656 using Synopsys PCI compliance suite. Can You Off A With? Worked on FIFO testing. There were 2 FIFOs.

One for thesis journal the Direct slave read and the other for the direct slave write. Wrote various test and verified the compare and contrast essay and outline functionality of the thesis FIFOs for both the empty and full condition. There were numerous condition to fill and empty the start off a FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. Thesis? The chip has 3 modes namely M, C and J modes . These modes are the local bus types. M mode is 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA.

January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). Essay Of Asian? The Hardware and Software Co- Verification helped in software debugging, shirk the journal system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the value of solitude essay product through a question/answer session and with follow up visits to potential customers. Thesis Journal? Performed evaluation of the product and against the product of cons humans competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x.

Advanced Networks, CA. December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the packet. Journal? The packets could be classified on the basis of the header or any byte of the data payload.

The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and nurses essay, non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to thesis journal verify the system bus interface using Verilog. Compare And Contrast And Outline? Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the thesis bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of role in health promotion a Networking SOC.

Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and thesis, HDLC. Was responsible for Verification of the bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC. Essay A Quote? Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes.

Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of journal a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the compare and contrast essay packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the NOC by writing the functional models in thesis, Verilog. Verified functional models.

Verified Packet buffer read and writing. Of Cloning Humans Essay? Packet buffer was read and written as 1024 bits at a time in journal, 11 clock cycles. Verified the compare and outline packet Queue (PQ) which performed queuing and dequeuing of the journal packet through the in a star address in thesis journal, PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model. Developed the test bench and wrote task for role promotion specific functionality. Developed test plans, test cases for the Chip Level Verification of the thesis ASIC using Verilog.

Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Verification of HDLC Controller (Project Lead) Involved in in a lab report, Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. Thesis Journal? The HDLC controller framed according to essay on stereotypes the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Journal? Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver.

Verified the HDLC. Synthesized the role essay HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to journal VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for essay on stereotypes LSI logic. Thesis? Was responsible for Conversion and Simulation.

Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96. Development of can you start with a quote Test Bench for BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by journal, Mentor Graphics. Start Essay With? The hardware (Verilog/VHDL) was simulated on journal, HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to can you a quote the processor and generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against thesis the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.

November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and on stereotypes of asian, the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in an 11-bit format to thesis journal the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. Essay? This also included the standard PC keyboard.

Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and thesis, CHIP layout. VLSI Logic design - Complete design flow from compare and contrast essay, RTL to thesis layout. Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in architectures of PCI OHCI. Proficient with USB. Knowledge in Unix, Perl and 'C'. Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and of cloning, Place Route. Configuring CPLD with bit blaster using MAX+plus II.

Expertise in Altera /APEX FPGA. Experience in Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools. Thesis? Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for nurses role APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. Thesis Journal? 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA.

Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Duration : May '97 - Apr '99. Designation : VLSI Design Engineer. Company : Analog Systems , Inc.

Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on can you off a, Oct '2001. The Total No. of gates is 1.2 Millions. It operates on 125 MHz.

It's a .18 micron technology. Journal? The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is nurses promotion essay, Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and journal, PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. Essay? The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and plenty of processing power are available for thesis the system vendor to cons of cloning essay provide differentiated value addition to the system. It is thesis, having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine.

The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Of Cloning Essay? Then for thesis the WAN interface we have 10/100 EMAC and of solitude essay, also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of thesis on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA. Developed the verification methods created testcases both normal corner for UART, SPI DMA.

Did the RTL netlist simulation for UART, SPI, DMA. With? Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at journal the system levels and also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in essay on stereotypes of asian, VERILOG. This s going to be used and cable modem chip.

The design was target for APEX FPGA from altera 20K200. The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from simultaneously from journal, 8 devices and gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to the memory . The data drain gets from compare and contrast essay and outline, memory and thesis journal, gives to the microprocessor module.

The design operates in 3 different frequencies. The input data is of cloning humans, coming at 10Mhz, which is to thesis the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for compare and contrast essay waveforms. Thesis Journal? Max-Plus II for P R. Synthesis by Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc. Location : Sacramento, CA. Designation : VLSI Design Engineer.

Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the Data from can you essay a quote, ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by thesis, the ATM fpga. Designed the code in value, Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech). Renoir Tool and thesis journal, Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage.

Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the humans essay memory for journal which the CPU provides the address. And Contrast And Outline? The data with the parity is then stored in the memory. While reading the data, it regenerates the parity and thesis, checks with the parity that is read. On error, the date is invalidated. The parity and data are stored in the memory through the interface. DMA is essay, used for reading and writing the data into the memory for burst of transaction.

Developed Designed the logic in verilog which is thesis journal, specific to Disk Module and essay, it provides the journal following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Start Essay With A Quote? Utopia1 slave is running on 25 Mhz and data rate is 53 bytes.

UTOPIA 2 master is running on 33 Mhz and thesis, date rate is 64 bytes. There are two downstream FIFOs and start, two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Journal? Module ware Utopia Master and Slave. Interface Data Path Between Tetra and on stereotypes of asian, SAR. Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of journal PFU. Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35.

Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the information about the device. Developed the PCI Test Bench for OHCI. And Contrast Essay And Outline? Created testcases for the functional verification of OHCI.

Host Controller is a device which serves devices attached to the USB bus. It is interfaced to the PCI bus for thesis journal accessing the system memory. Can You Start Off A Essay A Quote? Designed this core using both VHDL and thesis, VERILOG. This design has different types of modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98.

Designed OHCI compliant PCI master/target function. Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and essay on stereotypes, Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory. PCI target responds to configuration transaction's and thesis, other Bus Master's initiates transaction. Implemented the can you off a with logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator. Synthesized the logic using Exemplar's Leonardo tool.

Max+plus II tool is thesis journal, used for Place and start off a essay with, Route. Journal? Mapped the PCI core into essay the Altera Flex10k30 device. Mapped the USB side core into thesis the Altera Flex10k100A device. Mapping the whole design into ASIC Library and testing is in progress. Total gate count for OHCI project is compare, 33,000 gates.

Project : Design and thesis journal, verification of Hearsee-USB Logic. Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the essay and outline pixels and deliver the encoded data to the computer through USB. It consists of video camera interface, scalar, a high quality compressor and USB interface. The picture information coming from the camera is journal, processed by the hearsee block. This data is first scaled down by scalar block according to the mode of operation. This scaled down data is compressed by humans essay, the compressor block. This compressed form of thesis journal data is sent through the USB cable.

Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of lab report Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of a USB Device Core. Project : Design of FIFO. Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and thesis journal, latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device.

Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and essay of asian, Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of thesis Engineering (Electronics and Communication) 1997. Madras University, INDIA.

7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Microprocessor design and verification. Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of references in a lab report full chip and block level designs.

Functional verification of full chip design, Physical design skills at journal chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. Value Of Solitude? OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is thesis, a re-configurable processor with embedded ARC core mainly targeted at references in a lab report the networking applications. Responsibilities require me to write directed tests to verify the tile block and random tests to thesis journal verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the test vectors from the viewpoint of and contrast essay and outline code coverage, and furnish suggestions to the verification team as per the findings.

Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the thesis chip, e.g. Essay? fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the journal test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in compare and outline, automobiles for communicating between various controllers inside the vehicle. The project involved converting the journal latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing.

Responsibilities required me to convert the nurses role RTL to flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to journal be used in automotive Industry for anti-skid braking. It is based on in a lab report, Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and thesis, PR the Timer block. This project involved the cons of cloning full Network design cycle, except for RTL Coding. MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in journal, DSP engines.

The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block. Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the essay on stereotypes Full Chip functional Verification of the thesis microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the references in a test-bench for the full chip simulation. Later, the Compass-generated vectors were used to thesis journal generate the Verilog format vectors for full chip testing.

The work also involved the testing of essay on stereotypes vectors on the netlist generated by journal, the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is essay on stereotypes of asian, a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team. Redesigned 2 of thesis journal a series of 4 microcontrollers.

The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of cons of cloning essay expense to the company. Granada Consultancy Services. Assistant System Analyst. American Express Milleniax Conversion (10/97 - 03/98)

The project involved the thesis journal modification of the existing code for American Express to make it Y2K compliant. The project was divided in essay on stereotypes, various implementation Groups (IG's). Each IG was responsible for modifying and journal, testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader. Training in cons of cloning, Software Development Process (07/97 - 09/97) It involved training on thesis journal, different Software Platforms, Programming Languages and Graphical User Interface. Start Off A Essay With A Quote? It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000)

The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. It focused on advanced chip synthesis methods. 1997 B.Tech. in journal, Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of can you with a quote Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card.

Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in thesis journal, ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and off a essay, RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Thesis? Candidate in off a with, Computer-Aided Design Center, China. MSCE in Computer Engineering, WU, China. BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Rich experience in H/W and S/W co-design for MPU-based embedded application systems.

In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in journal, firmware programming in C/C++ under PC DOS, VxWorks and QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools. Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in Canada and China in and contrast, the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988.

These positions carry over 4-year real experience in thesis, ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada. 2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for can you start off a essay with the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design. Vermax Networks, Ottawa, Canada.

May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32.

It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and journal, data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Coded in of cloning humans essay, Verilog at RTL.

Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for thesis each block. Wrote simulation models and of cloning essay, performed min. function verification for top level with cores. Synthesized with Tcl scripts , and analyzed timing to journal fix timing issues at essay RTL and Gate level. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Defined software interface and supported firmware designers to thesis journal write ASIC driver.

Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an and outline ATM traffic scheduler.

It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and thesis, 20MHz. Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Developed and value of solitude essay, implemented the dynamical linecard, modem bandwidth allocation and sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers.

Implemented traffic congestion control based on modem and subport backpressure signals. Wrote the new version of the ASIC/FPGA design specification, verification and test plan. Thesis? Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions. Wrote model driver and testbench in Verilog and Vera to simulate each new block and top level. Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files. Used Synopsys 's DC and can you start with a quote, PT timing analysis for timing debug and timing closure. Wrote test script for VxWorks dshell and VisionICE to test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April.

ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in thesis journal, real world in cooperation of EE and CS departments. Successfully developed, implemented and tested the essay ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Thesis Journal? Defined functions of the essay on stereotypes of asian ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL. Designed an journal EDIF netlist core based PCI32 backend application interface in VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level. Synthesized by start off a essay a quote, Synopsys's Design Compiler. Timing debug and closure by Primetime.

Lab test by C++ programs developed to thesis test functions on a PCI32 FPGA prototyping board. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and compare and contrast essay and outline, Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench. CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Thesis? Verilog calculator design synthesized by references, Synopsys and implementation in Xilinx FPGA. Thesis? VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL. Co-supervised senior thesis: RISC design and implementation in can you start off a essay, Xilinx's FPGA. Real-time, multitasking programming in C using various semaphores for QNX real-time OS.

Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of journal MCU-based Controller for a graphic scanner. Synplify, Xilinx FPGA, OrCAD Schematic and cons humans essay, PCB, PC DOS and MCU programming in C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the new control algorithm. FPGA design in Xilinx F1.5, and thesis journal, board schematic and PCB design in OrCAD. PC DOS programming and MCU 8051 firmware programming in C. Digital Design Center, Wuhan, China.

1994 Sept - 1996 June. Ph.D. Role Essay? Project. Journal? Computer-based Non-contact Microsurface Online Measurement. Math algorithms and of asian, hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of thesis a team to develop a Computer Integrated Manufacture System (CIMS). Essay? Developing fast and precise online algorithms based on microscope and thesis, CCD sensors. Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.

Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and Processing System for customers. Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over cons of cloning humans 1000 points and are over 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Thesis Journal? Designed system scheme, circuit boards and firmware in on stereotypes of asian, C and debugged in labs. Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Hardware Engineer, Firmware Programmer. (Permanent full-time)

An electronic teaching laboratory Development. Schematic and PCB design in thesis journal, Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C. Developing an nurses electronic system to journal be used for value of solitude essay teaching spoken English. Leaded a team to design, test and install the journal electronic teaching laboratory for customers. Designed a PC-based host to control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals. Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W. Design a transmitter with Laser and a receiver with a coordinator to compare and contrast measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors.

Utilized a modulated Laser beam; Used 8031 MCU to be a controller and journal, programmed in C. Training Courses at Nortel Networks from 2000 to of asian 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Thesis Journal? Verification Strategies in Verilog High-Speed Circuit Design.

Primetime Training Workshop PowerPC 8260 Workshop. Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for of cloning essay VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and thesis, Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of on stereotypes of asian Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.

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4 Ways To Become A Deck Officer in Merchant Navy. Thesis Journal! As is with choosing any stream of education, selecting a career in Merchant Navy also requires a considerable amount of time devoted towards research so that a prospective individual is able to choose a course that best suits his needs. Value Of Solitude! Some might aspire to become deck officers whereas others might be interested in engineering knowledge. With a plethora of maritime institutes offering a variety of courses, it is natural for a candidate to get confused, and in thesis journal the process, make a wrong decision. There are myriad of references in a maritime institutes all over the world and it is thesis journal natural to be spoiled for choice. However, it is necessary to understand that not all of them offer the path to becoming a Deck Officer on ship in the way that it is imagined. Representation Image – Photograph by Jose Jacob. The role of cons of cloning a Deck Officer in merchant navy is indispensable on board and it is important for a prospective Cadet to know what a deck officer does on board ships.

A Deck Officer works in the execution of a variety of tasks- namely navigation and maneuvering of the vessel, handling of all safety equipment on board, and handing cargo, communications, and safety. All of thesis this seemingly daunting work is designated, divided, and handled among the Trainee Cadet, 3rd Officer, 2nd Officer, Chief Officer, under the on stereotypes, supreme supervision of the journal, Captain of the vessel. The prerequisites to join a maritime course pertaining to the Merchant Navy are generally kept low, except the physical fitness and medical requirements. However, it is advised that an interested individual inquire with the respective institute offering the in health essay, course in order to get the exact criterion. The following deck officer training courses outlined are those that will help an thesis journal individual a great deal in determining what’s best for value, a chosen path to becoming one. 1. B.S. Nautical Technology. This is a 3+1 years course that is available only in India.

The degree in question here is offered by the Birla Institute of thesis Technology and Science, Pilani, and is offered in two of the institutes in India. The first 3 years of the merchant navy course is spent in the institute where a variety of subjects are taught extensively. The final year is devoted to an internship on compare essay board a vessel as a deck cadet for a minimum period of 12 months. The internship period is extremely crucial as the degree is only conferred when an individual finishes his sea time. Thesis! The 2nd Mate license is obtained after finishing the mandatory sea time, upon clearing the MMD (Mercantile Marine Department) examinations.

There are a total of 48 subjects covered in the study period of 3 years, a detailed list of which can obtained from the website/brochure of the institutes concerned. Following are the can you start, institutes in India that offer this merchant navy program to thesis, become a deck officer: 2. B.Sc. Nautical Science. This is references a 3 years deck officer training course that is available in India. In the UK, this is a 4 years course. However, the method incorporated in the completion of this course varies between India and the UK. In India, a deck cadet spends his entire 3 years in a Maritime Institute and thesis journal, gets a degree after the course ends. Following that, he seeks employment and gets on board a ship as a Trainee Merchant Navy Deck Officer.

In the UK, work and learning are incorporated together within the course (a part of the deck officer recruitment process), with the core modules and work based learning divided aptly within the four years of study. Promotion! There are a host of thesis Institutes offering this merchant navy program, the notable ones being: 3. HND Nautical Science. HND stands for the Higher National Diploma. Can You Off A Essay! This is a 2 years course that is conducted between an thesis Indian Institute and one in the UK in liaison with each other. The first 39-40 weeks of the course is spent studying at an Institute in India whereas the next 39-40 weeks is spent at an Institute in the UK. Deck cadets must sail for a minimum period of 15 months after the completion of the course for the the deck officer cadetship. Essay Of Asian! Thereafter a 3 months 2nd Mate Preparatory course must be undertaken at thesis journal the deck cadets’ respective Institute.

Upon clearing the examination conducted by the MCA (Maritime and Coastguard Agency), the Cadet is awarded the 2nd Mate UK license to become a certified deck officer. The notable HND courses of merchant navy are conducted by: 4. Essay On Stereotypes! Diploma in thesis journal Nautical Science. This is a 1 year course under the Indian Maritime University. Prospective deck cadets undergo a year long period of study followed by a sailing period of a minimum of 18 months. There are many merchant navy institutes offering this course.

It is advisable to of solitude essay, check the Directorate General of Shipping and the Indian Maritime University websites for institute approvals and course details. In the United States, the Merchant Marine is a civilian auxiliary of the thesis journal, US Navy. The system followed in the US is a very intensive one. Candidates should refer to one of the Academy websites for a methodical procedure with regard to the US Merchant Marine. Check the list of best maritime colleges of the United States for more information. The most important aspect of choosing the right merchant navy Institute and course to become a deck officer is to ensure that the course is approved by the respective Government Authority of the country. It is also advisable to know the nation issuing the Continuous Discharge Certificate (CDC) to nurses in health, prevent any confusion later on. In addition to the above mentioned courses, several shipping companies also conduct sponsorship programs for deck officers. Choosing the right path to becoming a Deck Officer in merchant navy can play a vital role in having a solid kick-start to the career. Apart from thesis journal, good memories and in health essay, an unforgettable college life a proper institute, catered to journal, your requirements, can help an individual develop the right attitude towards this line of of solitude essay work.

It is to note that deck officer job description or deck officer salary mainly depends on thesis journal the shipping company. i got 56% pcm in role promotion 12th cbse , i want to journal, apply for references in a, DNS course . please guide me . Sir, how can i join merchant navy as a officer i have passed +2 in science and my age is 17. Correction: Kindly change the sailing time mentioned for the DNS Course. Now it is thesis 18 months instead of 36 months. I truly admire the efforts of MarineInsight as your articles are really helpful which shows the in a lab report, real life onboard ships. If possible, then please try to post articles regarding cruise ships and companies and the oppurtunities for an indian deck officers or engineers to get on passenger vessels. As, very few of us knew about it. Thesis! @ shubham and rahul - Check Academic Brochure 2016-17 on essay IMU Website which has all the details and guidelines. @Sagar: Thank You for the pointer.

We are not involved in Job placements and job sector. Thesis Journal! We will definitely post article on how to compare and contrast and outline, join cruise industry. Hello,sir my I'm a 12 years old boy my dream is to became a merchant navy officer so please help me to became a merchant navy officer#128591;#128591;#128583; Sir,if you have any tip to became a merchant navy officer please share it to me#128591;#128591; Sir, i ve passed 12th n i Want 2 join in merchant navy . What r the options 4 me . Plz reply. sir, I join Gp rating course kya Gp rating karne ke baad aage bade opportunity milte he plzz reply. Good morning sir, I have River master inland water and I want to upgrade myself to offshore please can I apply for Chief mate. And also DP. thanks best regard. Can I become a navigation officer after opting commerce (Maths) ? i want a favour and a help . and i want to know that i m 10 just pass 2017 , and i want to know the process to become deck offficer and for that what to do to achieve that. and now i m applining for gp rating cource . and can i move ahead for thesis, that? please help me sir. Hi sir my name b. Lokesh I completed in in health essay gP rating and 38 month's Saling completed I ask u how to prepare officer exam sir plz tell me. Apply for examination with all the required certificates and papers.

For other detail. Sir I've completed my secondary education with commerce stream. So can i go for any post in navy? You need to have PSM in 10/12th to join as deck or engineer officer. I am presently in journal class 12 commerce (with Maths). Can I join Merchant Navy as a Deck Cadet,and HOW.

Sir is there any way to directly become a captian in of cloning humans essay merchant navy. No. There is no shortcut to thesis, Success. Sir I am Raja from start essay a quote, Patna and I want to do a job in Merchant Navy. Thesis Journal! My Highest qualifications is B.Tech in Mechanical engineering. So please sir suggest me about my career in this field. The present situation of lack of job opportunities for deck cadets and junior marine engineers Merchant navy professionals working on compare essay ships are categorized into different departments and thesis, assigned with specific People planning to join Merchant Navy often ask us what is better – engine department On board ships, bosun is a very important member of a ship’s crew and his A shipyard career option is a very unique one.

Also since the can you off a a quote, shipbuilding process gets Want to join merchant navy after class 12th in India? Learn about journal different career options With several maritime jobs websites coming-up these days, it has become fairly easy to look

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essay good job which Read the topic and sample essay, then study the comments. Thesis Journal! Click on the highlighted text for of solitude, comments about academic writing conventions; click on the notes in the margin for commentary on the essay. Birth rates are falling in developed countries. Journal! There is one simple reason for this - young people nowadays are just too selfish and references in a lab report too self-centred to journal have children. And this is essay a quote, particularly true of women. Journal! To what extent do you agree with this view? Support your argument with relevant readings and evidence. Countries in the developed world have seen a big shift in attitudes to population growth. Several generations ago, it was generally believed that too many babies were being born, and that societies should try to reduce their populations.

Nowadays, however, the concern is the reverse - that birthrates are falling too low and that urgent action is needed to encourage people to have more children. But what are the causes of this trend? And how much are the attitudes and lifestyles of young people to blame? This essay will consider a number of compare and outline, explanations for the so-called baby crash. My argument will be that to hold young people responsible is neither valid nor helpful. The best explanation, I believe , is to be found in journal, the condition of increased economic insecurity faced by the young. The birth rate has fallen dramatically in many parts of the world. To take several examples, in Europe in 1960, the essay with, total fertility rate (TFR) was about 2.6 births per thesis journal female, but in 1996 it had fallen to 1.4 (Chesnais, 1998) . In many Asian countries, similar declines have been experienced. Japan now has a birthrate of only about 1.3, and Hong Kong#039;s has fallen to below 1.0 (Ichimura and essay Ogawa, 2000) . A TFR of journal, below 2.0 means that a country#039;s population is not replaced, and thus there is a net population decline.

This ageing of the population has the references in a lab report, potential to create serious problems. Fewer children being born means that in the long term, a smaller proportion of the populace will be economically productive, whilst a larger proportion will be old and thesis journal economically dependent - in the form of pension, health care and other social services. Most experts agree that these greying societies will not be able escape serious social and economic decline in the future (Chesnais, 1998). So what are the causes of this trend and what can be done to essay a quote stop it? One common approach has been to lay the blame on young people and journal their supposedly self-centred values. It is argued that in developed societies, we now live in a post-materialist age, where individuals do not have to be so concerned about basic material conditions to survive (McDonald, 2000a). Thus people, especially the young, have become more focussed on the values of self-realisation and the satisfaction of personal preferences, at the expense of traditional values like raising a family. A strong version of this view is put forward by Japanese sociologist, Masahiro Yamada (cited in Ashby, 2000) . He uses the term parasite singles to refer to grown children in essay, their 20s and 30s who have left school and are employed, but remain unmarried and continue live at home with their parents.

These young people are spoilt, he says, and interested only in their own pleasure - mainly in the form of shopping. According to thesis journal Yamada , it is this focus on self, more than any other factor, that is promotion essay, responsible for Japan#039;s languishing birth rate (Ashby, 2000). In other developed countries, there is a similar tendency for thesis, the young to remain at home enjoying a single lifestyle - and and contrast essay and outline a similar tendency for older people to interpret this as selfishness (McDonald, 2000a). But is it reasonable to attribute the baby crash to the pleasure-seeking values of the young? The problem with this view is that whenever young people are surveyed about their attitudes to family, not only do they say they want to have children, they also express preferences for family sizes that are, on average, above the thesis journal, replacement level (McDonald, 2000a).

As an example, McDonald quotes an Australian study that found that women aged 20-24 expected to have an average of 2.33 children in their lifetime. Findings like this suggest that the and contrast essay, values of the young are not at thesis, all incompatible with the idea of having a family. It seems then that, as young people progress through their twenties and of asian thirties, they encounter obstacles along the way that prevent them from fulfilling their plans to be parents. Some conservative thinkers believe the main obstacle is the changed role and status of journal, women (eg. Norton, 2003). According to this view, because young women now have greater educational and career opportunities than in previous generations, they are finding the idea of family and can you off a essay with a quote motherhood less attractive. Thus, educated middle class women are delaying marriage and childbirth or even rejecting motherhood altogether. It is claimed that women#039;s improved status - which may be a good thing in itself - has had the unfortunate consequence of threatening population stability. But there are several problems with this argument. For one, the lowest TFRs in Europe are found in Spain and Italy (around 1.2), both more traditional, male-oriented societies, which offer fewer opportunities to women. In comparison, Sweden which has been a leading country in advancing the rights of women enjoys a higher TFR (1.6 in 1996) - even though it is thesis, still below replacement.

Chesnais (1998: p. 99) refers to this contrast as the nurses role, feminist paradox and concludes that empowerment of women [actually] ensures against a very low birth rate (my emphasis) . Another problem with trying to thesis journal link improved education levels for women to low birth rates is that fertility in developed countries seems to be declining across all education and class levels. In a recent survey of Australian census data, Birrell (2003) found that, whereas the non-tertiary-educated group was once very fertile, its rate of lab report, partnering is now converging towards that of tertiary educated women. We can summarise the discussion to this point as follows: Young people today, in spite of what#039;s said about their values, still express a desire to thesis have children. However, few end up having as many as they say they would like. The improved education and career opportunities for women does not seem to be the decisive factor in reducing the number of children that a woman has. These conclusions suggest that there must be something else involved.

Many writers are now pointing to a different factor - the economic condition of on stereotypes, young people and their growing sense of insecurity. Peter McDonald (2000a) in his article #039;Low fertility in Australia: Evidence, causes and thesis journal policy responses#039; discusses some of the things that a couple will consider when they are thinking of having a child. One type of thinking is lab report, what McDonald calls Rational Choice Theory, whereby a couple make an assessment of the thesis journal, relative costs and benefits associated with becoming a parent. And Contrast Essay And Outline! In traditional societies, there has usually been an economic benefit in having children because they can be a source of labour to help the family. In developed societies, however, children now constitute an economic cost, and journal so, it is of solitude, argued, the benefits are more of a psychological kind - for example, enjoying the status of journal, being a parent, having baby who will be fun and will grow up to love you, having offspring who will carry on essay of asian, the family name etc. Thesis! The problem, McDonald suggests, is of asian, that for many couples nowadays the economic cost can easily outweigh any perceived psychological benefits. McDonald (2000b) discusses another type of decision-making - Risk Aversion Theory - which he says is also unfavourable to thesis the birth rate. According to this theory, when we make important decisions in our lives life, if we perceive uncertainty in our environment, we usually err on the side of nurses role in health promotion, safety in order to avert risk.

McDonald points to a rise in economic uncertainty which he thinks has steered a lot of journal, young people away from life-changing decisions like marriage and parenthood: Jobs are no longer lifetime jobs. Essay! There is a strong economic cycle of thesis journal, booms and can you off a busts. Geographic mobility may be required for employment purposes (McDonald, 2000: p.15). Birrell (2003) focuses on increased economic uncertainty for men. Referring to thesis journal the situation in in health promotion essay, Australia, he discusses men#039;s reluctance to form families in terms of perceived costs and risks: Many men are poor - in journal, 2001, 42 per cent of men aged 25-44 earnt less than $32,000 a year.

Only two-thirds of role promotion, men in this age group were in full-time work. Young men considering marriage could hardly be unaware of the risks of marital breakdown or the long-term costs, especially when children are involved (Birrell, 2003: p.12). And Yuji Genda (2000) in Japan, responding to Yamada#039;s analysis of thesis, parasite singles, argues that the failure of lab report, young Japanese to leave home and start families is not due to self-indulgence, but is an understandable response to increasingly difficult economic circumstances. Genda (2000) notes that it is the thesis journal, young who have had to bear the brunt of the decade long restructuring of the Japanese economy, with youth unemployment hovering around 10% and a marked reduction in secure full-time jobs for the young. Young people around the world seem to have an increasing perception of essay of asian, economic uncertainty and contemplate something their parents would have found impossible - a decline in living standards over their lifetime.

According to a 1990 American survey, two thirds of journal, respondents in the 18-29 age group thought it would be more difficult for their generation to live as comfortably as previous generations (cited in Newman, 2000: p.505). Furthermore, around 70% believed they would have difficulty purchasing a house, and references in a around 50% were worried about their future. Findings like these suggest that the younger generation may be reluctant to have children, not because they have more exciting things to journal do, but because they have doubts about their capacity to provide as parents. If we accept that economics has played a significant role in young people choosing to have fewer babies, then the key to reversing this trend is for governments to take action to remove this sense of insecurity. A number of policy approaches have been suggested. Some writers have focussed on can you, the need for thesis, better welfare provisions for families - like paid parental leave, family allowances, access to child care, etc (Chesnais, 1998). Others have called for more radical economic reforms that would increase job security and raise the living standards of the young (McDonald, 2000b). It is hard to know what remedies are needed. What seems clear, however, is that young people are most unlikely to reproduce simply because their elders have told them that it is selfish to do otherwise.

Castigating the of solitude essay, young will not have the effect of making them willing parents; instead it is thesis, likely to just make them increasingly resentful children. Ashby, J. (2000). Parasite singles: Problem or victims? The Japan Times. Start With! 7/04/02.

Birrell, B. (2003). Fertility crisis: why you can#039;t blame the thesis, blokes. The Age 17/01/03 p. 14. Chesnais, J-C. (1998). Below-replacement fertility in value essay, the European Union: Facts and Policies, 1960-1997. Review of Population and Social Policy, No 7, pp.

83-101. Genda, Y. (2000). A debate on thesis, Japan#039;s Dependent Singles, Japan Echo, June, 2000, pp. 47-56. Ichimura, S. and N. Ogawa (2000). Policies to meet the challenge of an aging society with declining fertility: Japan and other East Asian countries. Paper presented at the 2000 Annual Meeting of the Population Association of America, Los Angeles, USA.

McDonald, P. (2000a). Low fertility in Australia: Evidence, causes and can you with policy responses. Thesis Journal! People and essay of asian Place, No 8:2. pp 6-21. McDonald, P. Journal! (2000b). The toolbox of lab report, public policies to impact on fertility - a global view. Paper prepared for the Annual Seminar 2000 of the European Observatory on Family Matters, Low Fertility, families and Public Policies, Sevilla (Spain), 15-16 September 2000. Norton, A. (2003). Student debt: A HECS on fertility?

Issue Analysis No 3. Journal! Melbourne: Centre for can you off a essay, Independent Studies. Newman, D. (2000). Sociology: Exploring the architecture of everyday life. California: Pine Forge. Notice what the question is asking students to do - in this case saying how much they agree with the #039;view#039; in the topic. Thesis Journal! What do you think? Is this a reasonable explanation for the declining birthrate? Hint: always spend some time looking over essay, and thinking about an essay topic before you start your planning and reading for it.

As part of this thinking, you should give some thought to what your position (argument) could be. Notice how in the introduction, this student writer: introduces the topic area in a general way (ie. Thesis! declining birthrates) introduces the main issue to be covered in the essay (ie. why this is happening). Hint: there are many different ways you can begin an and outline essay - if you are stuck, try beginning with i) and ii). In the last part of the introduction, the student introduces his argument. Notice how he disagrees with the explanation in the topic, and then offers an alternative explanation. Hint: in the introduction it is always a good idea to state what you intend to journal argue. In this paragraph, the student considers the first part of the topic - that birth rates have fallen. This is presented as background information. Notice how the student begins the paragraph with a claim (that the birth rate has fallen dramatically in many parts of the world) and then supports this with relevant evidence (statistics from Europe and Asia). Hint: in your writing be aware when you are making claims - be aware also of the need to can you essay a quote support them with some evidence. After giving some background in paragraph 2, the thesis, student reminds the reader what the main issue is - why birthrates have declined?

Notice also that the student has seen the issue as a #039;problem#039; - and essay asks What can be done about it? Hint: always be aware what the main issue is you are addressing in your work. This paragraph mainly summarises the ideas of those who think young people are to blame for declining birthrates. Notice how in the first part of the paragraph, these ideas are discussed in a general way. In the second part, the student focuses on journal, the ideas of a single writer (Yamada) as a specific example of this view. Hint: always try to find opportunities in your work to engage with the ideas of value, individual writers. The previous paragraph was concerned with summarising some ideas. Notice how in this new paragraph, the student provides a critique of thesis, these ideas. (Recall the student#039;s argument in and outline, the introduction: . to hold young people responsible is neither valid nor helpful). Notice too that the student provides some supporting evidence for journal, this critique - mainly from the work of McDonald. Hint: it is quite OK to criticise the ideas of other writers - in value of solitude essay, fact many essay topics will specifically ask you to do this. But if you are going to be critical, you need to provide good reasons for your critique.

Recall that the topic suggested that young people were to blame for declining birthrates - and then went on thesis journal, to single out women. In this paragraph, the student takes up this gender issue. Hint: aim to structure your essays so that all issues in the topic are covered - and in some logical sequence. In this paragraph the student seeks to dismiss the view that young women are to blame. (There are several problems with this argument).Notice that the student then goes on to explain these problems (For one. ; Another problem is that . ). Hint: the providing of a well-organised critique is something your lecturers will value highly in your work. Recall the second part of the student#039;s argument stated in the introduction: The best explanation is to be found in the condition of increased economic insecurity faced by the young.

The student now elaborates on this part of the argument. Hint: remember that the argument is the key to any essay you write. In the body of your essay, you need to be sure that your argument comes through clearly. Providing evidence for the argument. The student is arguing that economic insecurity experienced by young people is the main reason why the birthrate is in essay on stereotypes, decline. Journal! Notice how in the rest of the essay, he seeks to support this argument with various forms of evidence. The student presents a range of evidence: several theories discussed by McDonald some research by Birrell comments by Genda results of a US survey. Hint: it is essay on stereotypes, important to have an argument in journal, your essay. But it is equally important to on stereotypes of asian provide support for what you are arguing. Your essays will be judged mainly on your ability to do these two things. There are a number of things happening in the conclusion.

In the first sentence, the student restates his argument - if we accept that. . He then goes on to discuss what could be done to deal with the problem. In broad terms this is a discussion of the implications of the students#039; argument. Notice also how the thesis journal, student mentions the negative implications of the blaming approach. Hint: a conclusion that only restates the argument can be a bit uninteresting. You might also like to value of solitude consider the implications of your argument - but you should do this briefly.

Think: I have argued for this position - so what might follow on from this. You may have noticed that this essay is quite tightly structured. Its paragraph structure can be set out thus: Introduction Background to thesis journal issue Explanation point 1 - summary student#039;s critique Explanation point 2 - summary student#039;s critique Student#039;s alternative explanation - Evidence 1 - Evidence 2 - Evidence 3 Conclusion. Hint: always try to map out a structure for essay and outline, your essay. Do this before you do too much writing. You may have noticed that the essay is free of spelling, typographical and grammatical errors.

Hint: always read your work very carefully before you submit it. Avoid doing your editing on the screen. Thesis! Always print out and start off a a quote edit from a hard copy. Note in the references section, you need to list all the texts you have referred to (cited) in thesis, the essay - not all the texts you have read, as some students mistakenly believe. Notice that the sample essay refers to a total of nurses, nine texts. Thesis! This is references in a lab report, a good number, and indicates that the student has done a fair amount of reading. Hint: try to include a reference to most of the texts that you read for an essay - so that you can build up a reasonable list of journal, references. Of course, all references have to of asian be relevant to thesis your argument.

Notice how the student uses I in his essay: The best explanation, I believe, is. And in compare and contrast essay and outline, the previous sentence, another first person pronoun is thesis journal, used: My argument is that . Some students have the impression that they are not allowed to use these words in their written work. But in fact they can often be found in essay, academic writing. In general, the thesis, best place to use them is in the introduction - when you are presenting your argument. But if you are concerned that it is not OK to use I, you can use other expressions - which avoid self-reference, but which mean much the same thing, e.g. This essay will argue that . Remember though, that the really important issue is not the words you use to present your argument - but that your essay actually has a clear argument. Try to keep your paragraphs a reasonable length. (Most paragraphs in this essay are around 7-8 sentences long.)

Citations are used to indicate the source of the start with, ideas you have used in your essay. Note that there are two main citation systems: the author-date system (also known as Harvard); the footnote system (also known as Oxford). In this essay, the author-date system has been used. (Always check which system is required in each of thesis, your subjects.) Citation 2 (Ichimura and Ogawa, 2000) Citations can be set out in a number of ways. One method is to cons of cloning essay present some information and then provide the citation immediately after it to indicate the source.

These are known as #039;information-prominent#039; citations eg: Japan now has a birthrate of only about 1.3, and Hong Kong#039;s has fallen to below 1.0 (Ichimura and Ogawa, 2000). Other formats are considered further on. Citation 3 Masahiro Yamada (cited in Ashby, 2000) This citation means that the student is dealing with the ideas of thesis, Yamada, but actually read about them in Ashby#039;s text. Value Of Solitude! Whilst you should make an effort to read ideas in their original form, this is not always possible. In such cases, use the #039;cited in#039; format. When you are summarising the journal, ideas of a writer, you need to use reporting expressions like the ones used here:

He [Yamada] uses the term . According to can you with Yamada. You use these to distance yourself from certain language. eg. when you are using an informal expression, or a term used by others that you don#039;t necessarily agree with. In this paragraph, the student wants to reject the view in the topic - that young people#039;s selfishness is to blame for the declining birthrate. Thesis Journal! Notice how he does this in a careful way, by on stereotypes, using expressions like: Findings like this suggest that . It seems then that . Being careful about the way you express your claims is a distinctive feature of academic style. When you quote an author (like Chesnais here) you need to use quotation marks, and indicate the exact page number in the citation. Sometimes you may need to change the wording of the quote slightly so that it fits into your sentence. If you need to add/change any words, use [ ]; if you need to delete words, use . (Whilst it is OK to change the thesis, wording of a quote, you must never change its sense.) Use italics when you want to emphasise a word. (When you do this in a quote, you need to indicate that it is your emphasis.) It#039;s OK to use dot points in an essay (or numbered points here), but use them very sparingly.

Citation 4 Peter McDonald (2000a) . discusses. Notice how in value of solitude, some citations the author can be part of the sentence: Peter McDonald (2000a) . discusses some of the things etc. This is known as an #039;author-prominent#039; citation and journal is very common in academic writing. Notice the use of reporting verbs in this citation type (discusses). Use #039;inverted commas#039; for the title of an article. Use italics for references, the title of a book. Notice some of the other reporting expressions used in the student#039;s summary of Peter McDonald#039;s ideas: . what McDonald calls. . Thesis Journal! McDonald points to . . which he thinks. It#039;s very important to make it clear to your reader when one paragraph ends and a new one begins. In this paragraph (#9), there is some potential for confusion.

Notice how the student has used indenting to make this clear. Quotes of more than one sentence in length should be separated from the main text. Compare And Contrast And Outline! Notice how these are indented and are in thesis journal, a slightly smaller font. Again you should indicate the page number. You only on stereotypes of asian, have to provide a separate list of thesis, references when you use the author-date system. Entries should be set out in alphabetical order. Each entry should generally be set out in the following order and format: Author family name, Initial. Nurses Role In Health Essay! (date). Title. Place: Publisher. It is becoming increasingly common for students to refer to thesis sources from the world wide web in with a quote, their essays. In addition to providing author and title of site, you need to include: the URL for thesis journal, the site when you accessed the site.

Although web references can be very useful, you obviously need to exercise some caution - there is a lot of humans essay, junk around. Check all sites carefully to thesis be sure the lab report, information provided has credibility (.edu and .org sites are generally the more reliable). Problems? Questions? Comments?

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